1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a programmable read-only memory device wherein each memory cell comprises a transistor (referred to as a floating gate transistor hereinafter) having a floating gate and a control gate formed above the floating gate, and data can be programmed into the floating gate transistor reliably even at a low programming voltage.
2. Description of the Prior Art
Recently, the programming voltage for an EPROM (erasable programmable read-only memory) having a floating gate transistor as a memory cell has been lowered. This is mainly because transistors in a peripheral circuit are micropatterned and have a low breakdown voltage to realize a high density memory device, and the programming voltage must be lowered in accordance with such a reduced breakdown voltage. However, when the programming voltage is lowered, a programming current is also reduced to realize a high memory density memory device. As a result, data may not be properly programmed into a memory cell. For this reason, the peripheral circuit or the like must be improved to ensure that data is properly programmed into the corresponding memory cell.
In a conventional memory device, data is programmed into a memory cell, i.e., a floating gate transistor, by applying high voltages to the control gate and the drain of the transistor. However, since the application timings of the high voltages are not particularly determined, the programming operation of the floating gate transistor is not properly performed, especially when the high voltage is applied to the drain after it is applied to the control gate, or after the control gate voltage becomes relatively high.